Chip density increase is slowing down. Since N10, density scaling has been 60-80%. N3 to N2 is only 20%. And now N2 to A14 is also only 20%.

I can’t believe we’re talking Angstroms already.

TSMC: <a href="https:&#x2F;&#x2F;www.tsmc.com&#x2F;english&#x2F;dedicatedFoundry&#x2F;technology&#x2F;logic&#x2F;l_A14" rel="nofollow">https:&#x2F;&#x2F;www.tsmc.com&#x2F;english&#x2F;dedicatedFoundry&#x2F;technology&#x2F;log...</a><p>Not sure what this source is, but it looks sketchy.

In simpler terms, the SRAM density improved by 2.9% (according to ChatGPT). Which is better than it sounds, because SRAM had reached a wall, in terms of density gains, and, chips can be dominated by SRAM in terms of surface area, so this can mean a lot more room for logic, even though that is also getting considerably denser.

Come on we&#x27;re in the 21st century, UTF-8 is pervasive. Just call it &quot;Å14&quot; node.

Abstract at IEDM website below<p>ABSTRACT<p>A14 NanoFlexTM Pro platform technology features the world’s smallest SRAM with a cell size &lt;0.017μm2 and highest SRAM macro density to date through dimensional ground rule scaling. Coupled with standard cell innovations, it delivers a full-node PPA improvement over the predecessor N2 technology for a 10~15% speed enhancement, a 25~30% power reduction and a chip density increase by ~20% driven by logic and SRAM scaling. Key features, such as TSV, innovative RDL that enables SoIC bond pitch of 4.5μm and high-performance MiM processes, have also been developed to accelerate the system-level integration and scaling for SoIC products. Supported by robust yield and device progress, A14 technology is on track for volume production in 2028.

HN

TSMC revealing details about next gen A14 node

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