Lore – Open source version control system designed for scalability

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Hey HN! I&#x27;m Zach from Adam (<a href="https:&#x2F;&#x2F;adam.new&#x2F;">https:&#x2F;&#x2F;adam.new&#x2F;</a>). We&#x27;re building AI agents for mechanical CAD software. We’ve built the company on two fundamental beliefs:- AI will be the primary medium for creating mechanical designs just like it is in software today.- The best paradigm for CAD generation is to generate CAD as code (text -&gt; code -&gt; CAD).We’re building CADAM, an open source Text to CAD platform. It&#x27;s a React app (TanStack Start) with a Supabase backend for auth, database, and file storage. Think of it like AI TinkerCAD.Demo: <a href="https:&#x2F;&#x2F;www.youtube.com&#x2F;watch?v=iESOr7EGWqk" rel="nofollow">https:&#x2F;&#x2F;www.youtube.com&#x2F;watch?v=iESOr7EGWqk</a>
Try it: <a href="https:&#x2F;&#x2F;adam.new&#x2F;cadam&#x2F;">https:&#x2F;&#x2F;adam.new&#x2F;cadam&#x2F;</a>What it does:- Generates parametric 3D models from natural language, with support for both text prompts and image references.- Outputs OpenSCAD code with automatically extracted parameters that surface as interactive sliders for instant dimension tweaking- Exports as .STL or .SCAD (plus OBJ, GLB&#x2F;GLTF, FBX, and DXF)Under the hood:- One agentic endpoint with two modes that swap system prompts and tools: a parametric mode that writes&#x2F;edits OpenSCAD via a build_parametric_model tool, and a mesh mode that generates 3D textured meshes.- Simple parameter tweaks bypass the model entirely; adjusting a slider does a deterministic regex update on the SCAD source, requiring no LLM call.- Model-agnostic via the Vercel AI SDK: Anthropic (Claude), Google (Gemini), and OpenAI&#x2F;others through OpenRouter, with adaptive thinking auto-enabled on newer models. Surprisingly, in our evals Gemini 3.1 Pro is the top model.- Runs fully in-browser by compiling OpenSCAD to WebAssembly (in a Web Worker, so the UI never blocks) and rendering with Three.js via React Three Fiber- Supports BOSL, BOSL2, and MCAD libraries, plus custom font support (Geist) for text in modelsFuture improvements:- Support both build123d and CadQuery. This will allow us to move beyond CSG primitives to constraint-driven modeling and provide direct comparisons to other code-as-CAD primitives.- Better spatial context: UI for face&#x2F;edge selection and viewport image integration to give LLMs spatial understandingYou can clone the repo and run it locally! Contributions are very welcome.

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I hate compilers

Hi! me and my friends together built an 8 bit CPU implemented in Logisim purely from scratch. The control unit of this system does not implement the generic microcode ROM or any kind of RAM. This was made purely from discrete logic gates and coded the system to run different programs.key features:
Custom 16-instruction Harvard ISA, 8-bit fixed 
format, 4 general purpose registersHardwired control unit built entirely from AND&#x2F;OR gate logic matrixDual-phase clocking to eliminate race conditionsBootstrap Control Unit that cold-boots via ROM-to-RAM transfer
Early-exit conditional branching that saves upto 25% cycles when conditions aren&#x27;t metFull design specification document with version controlSince this was our first time doing such teamwork and a new thing we used RISC based system that fetches an 8-bit instruction from Instruction memory 4 bits of which translate to an instruction the last two bits are for source and destination registers. 
There are a total of 4 registers in the system with two memory units namely Data SRAM and I SRAM, the system follows a Harvard architecture.There are design discrepancies too since it was our first time designing such a system and on top of that completely hardwired too.To solve the problem of cold booting a bootloader is present too that copies the contents of a temporary ROM into instruction RAM and then hands over the reins to the CPU.We also implemented conditional branching as well as early exit branching too that only checks for zero or carry flag and branches without wasting cycles, if the conditions are not met the Program counter increments.Moreover we also created a complete documentation with version control describing each necessary part assuming prior knowledge.Please take a look at it at <a href="https:&#x2F;&#x2F;github.com&#x2F;c0rRupT9&#x2F;STEPLA-1" rel="nofollow">https:&#x2F;&#x2F;github.com&#x2F;c0rRupT9&#x2F;STEPLA-1</a>For future development I want to implement a RISC CPU using FPGA&#x27;s and connect it to an actual DRAM. We are also selling the full spec document and Logisim files for $5 to fund our passion
<a href="https:&#x2F;&#x2F;tcfdiq.gumroad.com&#x2F;l&#x2F;zyyux" rel="nofollow">https:&#x2F;&#x2F;tcfdiq.gumroad.com&#x2F;l&#x2F;zyyux</a>
Thankyou!

Show HN: We built an 8-bit CPU as 2nd year EE students

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